1. Field of the Invention
This invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of preventing occurrence of erroneous operation due to noise.
2. Description of the Related Art
In the conventional semiconductor integrated circuit, for example, EPROM, write enable signal WE of active-low (that is, which becomes active at a low level) is supplied from write-in control circuit 51 to circuit block 52 as shown in FIG. 1 in view of the arrangement of the memory blocks. Data write-in operation is effected in circuit block 52 in response to signal WE.
FIG. 2 shows the schematic construction of the circuit block 52 of a conventional electrically data programmable nonvolatile semiconductor memory (EPROM). In FIG. 2, memory cells MC1 to MCn are each formed of a memory cell transistor. FIG. 3 is a cross sectional view showing the construction of memory cell MC1. Source 72 and drain 73 formed of n+-type diffusion regions are formed in the surface area of p-type substrate 71, floating gate 74 is formed above that portion of the substrate which lies between the source and drain, and control gate 75 is formed above the floating gate. The film thickness of that portion of insulation film 76 which lies between substrate 71 and floating gate 74 is set to tox1 and the film thickness of that portion of insulation film 76 which lies between floating gate 74 and control gate 75 is set to tox2.
Since the EPROM is a nonvolatile memory, data programed into memory cell MC1 can be permanently stored unless all the stored data is erased by application of ultraviolet rays. In this case, the "data programming" means that electrons are injected into floating gate 74 of memory cell MC1 and data of the memory cell is set to "0". That is, memory cell MC1 having data of "1" is not programmed and set in the erasing state in which no electron is injected into floating gate 74 of the memory cell MC1. For this reason, in order to program data into the memory cell, high voltage for programming is simultaneously applied to drain 73 and control gate 75 of the memory cell which is desired to store data "0", thereby causing hot electrons to be injected into the floating gate from the channel between drain 73 and source 72. As a result, the threshold voltage of the programmed memory cell transistor is raised and thus data is programmed into memory cell MC1 of the EPROM. The programming operation is effected by use of an exclusive-use device which is called an EPROM writer. The EPROM is mounted on a device using the EPROM after the programming operation.
In the readout mode, voltage Vcc of 5 V, for example, is applied to control gate 75 to read out data stored in memory cell MC1.
As described above, in the EPROM, the level of a voltage applied to control gate 75 when data is programmed into data storing memory cell MC1 is different from that applied when data is read out from the memory cell. For example, voltage Vcc (5 V) is applied in the data readout operation, and voltage Vpp (12.5 V) is applied in the data programming operation. Therefore, it is necessary to provide a switching circuit for switching voltages Vcc and Vpp in addition to externally supplied power source voltages Vcc (5 V), Vpp (12.5 V) and Vss (0 V).
As shown in FIG. 2, the switching between voltages Vcc and Vpp is effected by use of voltage switching circuit 102. Switching circuit 102 is supplied with normal data readout voltage vcc via terminal 142 and data programming high voltage Vpp via terminal 144 and selectively supplies voltage Vcc or Vpp as voltage SW according to an programming control signal (write enable signal). Voltage Vpp is also supplied to programming control section 104. Programming control section 104 includes transistor 134 whose drain and source are respectively connected to terminal 144 and column selection gate circuit 108 and programming control buffer 132 connected to receive voltage vpp as a power source voltage for controlling the gate voltage of transistor 134 according to programming data Din.
Column decoder 106 decodes a column address included in the input address to output the decoded result to column selection gate circuit 108. Circuit 108 includes a plurality of N-channel MOS transistors and selects memory cell MC1 based on the decoded result of decoder 106. Row decoder 110 decodes a row address included in the input address to output the decoded result to row address buffer 112. Buffer 112 is supplied with voltage SW from circuit 102 as the power source voltage and supplies a voltage to control gate 75 of memory cell MC1.
The drain and source of memory cell MC1 are respectively connected to ground voltage terminal Vss and bit line 120. Bit line 120 is connected to one input terminal of sense amplifier 116 via a plurality of transistors of column selection gate circuit 108. Sense amplifier 116 senses "1" or "0" of data stored in memory cell MC1 by comparing the potential of bit line 120 varying according to data stored in one of memory cells MC1 selected by row decoder 110 and column decoder 106 with an input reference voltage to be described later.
Reference voltage generation circuit 122 supplies a reference voltage to sense amplifier 116. Circuit 122 includes dummy cell DC constructed by the same memory cell transistor as memory cell MC1, dummy bit line 118 and column selection gate circuit 114 having normally turned-on transistors of the same number as the transistors series-connected in column selection gate circuit 108. The level of the reference voltage is determined by turning on dummy cell DC. In order to obtain a stable reference potential, it is necessary to design the transistor characteristics of memory cell MC1 and dummy cell DC equal to each other.
With the above construction, when data is programmed into memory cell MC1, high voltage Vpp is supplied as voltage SW from power source switching circuit 102 to row address buffer circuit 112. At the same time, high voltage Vpp is supplied from programming controlling buffer 132 to the gate of programming controlling transistor 134. If the threshold voltage of transistor 134 is Vth, a voltage of (Vpp-Vth) is supplied to the drain of memory cell MC1 via column selection gate circuit 108. Further, high voltage Vpp is supplied from row address buffer 112 to the control gate of memory cell MC1. As a result, current flows in the source-drain path of memory cell MC1, causing hot electrons to be injected into floating gate 74 to raise the threshold voltage of memory cell MC1. In this way, data is programmed into memory cell MC1.
When data is read out from memory cell MC1, voltage Vcc is supplied as voltage SW from power source switching circuit 102 to row address buffer 112. At this time, voltage Vcc is supplied from row address buffer 112 to the control gate of memory cell MC1, permitting a voltage corresponding to data stored in memory cell MC1 to be supplied to sense amplifier 116 via column selection gate circuit 108. A reference voltage is also supplied from reference voltage generating circuit 122 to sense amplifier 116. Then, sense amplifier 116 compares the voltage supplied from memory cell MC1 with that supplied from dummy cell DC and outputs the comparison result as readout data to the data line.
It is necessary to remove the EPROM into which data has been written or programmed from the socket of the writer and insert the same into the socket on a board of a device on which the EPROM is to be mounted. In this case, an electrostatic serge may be applied to pins of the EPROM while the EPROM is removed from the socket, transferred and inserted into another socket. A protection circuit is provided to protect the internal circuit from being damaged by an externally applied serge. However, there is a possibility that data may be erroneously programmed into the memory cell in a case where a surge is applied to a vpp power source pin. Now, the erroneous data write-in or programming is explained.
FIG. 4 shows the construction of power source switching circuit 102 provided in circuit 52 of FIG. 2. MOS transistors 53 and 54 are each formed of a depletion type N-channel MOS transistor. The drains of transistors 53 and 54 are respectively connected to Vpp power source terminal 144 and Vcc power source terminal 142, and the sources thereof are commonly connected to node 23. As described before, voltage SW at node 23 is applied to the control gate of memory cell MC1 and the like. Signal SW is directly supplied to the gate of transistor 54 and to the gate of transistor 53 via potential conversion circuit 58. Potential conversion circuit 58 serves to convert a Vcc system signal ("H"=5 V, "L"=0 V) into a Vpp system signal ("H"=Vpp, "L"=0 V) and is supplied with Vpp and ground voltage Vss (0 V) as a power source voltage.
One of Vpp and Vcc power source voltages is selected by means of voltage switching circuit 102 in response to signal WE. In voltage switching circuit 102, signal WE is set at logic level "L" and an output of potential conversion circuit 58 is set to logic level "H" in the data write-in mode. As a result, high voltage Vpp is applied to the gate of transistor 53 to turn on the same. Further, signal WE of logic level "L" is directly applied to the gate of transistor 54 to turn off the same. Therefore, high voltage Vpp is transmitted to node 23 via transistor 53, thereby applying high voltage Vpp to the control gate of memory cell MC1. In contrast, in the readout mode, transistor 54 is turned on and transistor 53 is turned off, causing voltage Vcc to be supplied to node 23 via transistor 54. As a result, voltage Vcc is applied to the control gate of memory cell MC1.
Assume now that a serge is applied to the Vpp power source terminal and the potential thereof is raised when all the pins of the EPROM are set in the electrically floating state. In this case, in power source voltage switching circuit 102 of FIG. 4, parasitic capacitor C1 exists between the drain and gate of transistor 53 and therefore the gate potential of transistor 53 is also raised to a high potential by capacitive coupling. As a result, transistor 53 is turned on to raise the potential of node 23. Further, since parasitic capacitor C2 exists between the source and gate of transistor 54, transistor 54 is also turned on in the same manner as in the case of transistor 53 and the potential of power source Vcc supplying terminal 142 which is externally set in the floating state is raised to a high potential level.
When a voltage at terminal 142 is raised to a certain level, for example, 2.5 V, the internal circuit starts to effect the normal operation. Even when the internal circuit starts to effect the normal operation and a high voltage is applied to terminal 144, the write-in mode cannot be always set because the other control pins are still in the floating state and the potential thereof is not determined. However, the potential level to which the potential of each node of the internal circuit is transiently set by means of the above-described parasitic capacitor of the transistor when the potential of terminal 142 is raised cannot be determined, and there is a possibility that the internal circuit is set into the write-in mode irrespective of the input potential of the control pins. In this case, the potentials of the drain and control gate of a memory cell designated by an address which happens to be internally set up are raised to a high potential level, causing electrons to be injected into the control gate and effecting the data write-in operation.
Application of a serge is effected instantaneously and therefore time in which the memory cell is kept in the write-in state cannot be always sufficiently long in comparison with the ordinary write-in time. Further, the potential of node 23 cannot be always sufficiently high for the data write-in operation depending on the potential level by which the potential of the gate of transistor 53 is raised. However, even if the write-in time, and the potentials of the drain and control gate of the memory cell are insufficient, the threshold voltage of the memory cell will be changed if electrons are injected into the floating gate. In this case, if variation in the threshold voltage is large so that data "1" can be stored into the memory cell, data of the memory cell which should be set in the erased state is changed to "0", causing a serious error. Further, even if variation in the threshold voltage is small, it becomes difficult to read out data "1", causing the access time in the data readout mode to be degraded.
The above problems may easily occur in a case where signal WE whose "L" level is significant (active) is supplied to a circuit block. As the length of a wiring for transferring signal WE becomes longer, the capacitor between the wiring and the substrate becomes larger. As a result, the potential of the wiring tends to be pulled down to the substrate potential or ground potential by means of the capacitive coupling between the wiring and the substrate. Therefore, when the length of the wiring is long, even if write enable signal WE is set to "H" level, signal WE tends to be pulled down to the ground potential, thereby setting the write enable state. As a result, there is a high possibility that the internal circuit is set into the write-in state when the internal circuit is instantaneously operated by a serge as described before.
Further, in an ordinary semiconductor integrated circuit as well as an EPROM, a control signal whose "L" level is set as a significant potential level tends to be pulled to "L" level potential by the capacitive coupling between the wiring and the substrate in a case where the control signal of "H" level is transmitted along the wiring formed on the substrate set at the ground potential and in this case the internal circuit may be erroneously operated.